In semiconductor device manufacturing, 3D monolithic designs may include stacked layers of devices (e.g., field effect transistor (FET) devices) that are sequentially processed to reduce a device footprint. For example, a FET-over-FET integration scheme is one form of 3D monolithic integration in which p-type and n-type FET devices are separately formed on different device layers of a 3D monolithic semiconductor IC device. The separation of p-type and n-type FET devices provides certain advantages such as the ability to use more optimal or compatible semiconductor materials (e.g., germanium, silicon-germanium, silicon, group III-V compound semiconductor material, etc.) on different layers to enhance or otherwise optimize device performance.
Monolithic 3D semiconductor IC devices are fabricated using one of various conventional methods. For example, one conventional process involves fabricating a lower device tier with FET devices, and then bonding a semiconductor substrate (e.g., pristine silicon layer or silicon-on-insulator (SOI) substrate) to the lower device tier, followed by upper layer device processing to fabricate FET devices on the semiconductor substrate and connections to the lower device tier. Power delivery distribution networks for conventional 3D monolithic designs typically have parallel power busses (e.g., VDD and ground) that are formed as part of a metallization level (e.g., M2) of a back-end-of-line (BEOL) interconnect network. Vertical interconnects are formed to route ground and VDD connections from the upper power busses in the BEOL interconnect network to the underlying device tiers (or lower and upper device tiers). In addition, in each tier, a network of parallel lateral connections (e.g., power straps) are formed as part of, e.g., middle-of-the-line (MOL) metallization to route VDD and ground connections to the FET devices.
Such conventional power distribution network solutions for 3D monolithic IC designs are problematic for various reasons. For example, conventional power distribution networks typically occupy a substantial amount of area in each device layout cell, which limits integration density. In addition, the network of lateral connections, which are formed in the device layout cells in the upper and lower device tiers to laterally route the vertical power (e.g., VDD) and ground connections which are routed down from the BEOL layer, have relatively high resistance, resulting in higher power dissipation.